Ireland still set for FinFETs, says Intel exec

Ireland still set for FinFETs, says Intel exec

LEIXLIP, Ireland – Intel's wafer fab campus here is still on course to run a 14-nm FinFET manufacturing process despite the return to Ireland of a large number of workers that had been on assignment at Intel sites in the U.S. for training, according to the general manager of Intel Ireland.

When asked if Intel Ireland was still planning to introduce a 14-nm FinFET manufacturing process – or tri-gate as Intel calls it – at Leixlip in 2013, Eamonn Sinnott, vice president and general manager of Intel Ireland, said there is no delay and no change to the process introduction schedule in Ireland. However, Sinnott declined to give any indication of what schedule, if any, is in place.

The Irish Times recently reported that Intel was sending up to 600 Irish staff home early from production training in the U.S. after deciding to delay the introduction of the P1272 14-nm process at Fab 24 in Leixlip. The newspaper reported that the ramp of 14-nm production in Ireland had been pushed out six months to late 2013, attributing the delay to a slowdown in demand rather than technical problems. Intel is also planning to ramp P1272 at Fab D1X in Oregon and at Fab 42 in Arizona.

"The sending home is not related to plans to introduce 14-nm," Sinnott said during a press tour of the Leixlip campus. He added: "Paul Otellini [CEO of Intel] has identified Intel Ireland on the roadmap for the introduction for 14-nm."

At present Fab 24 is manufacturing a variety of logic chip sets on 65-nm CMOS process technology, a mature technology for Intel that could be phased out relatively soon. Intel's Fab 24 is running the same process as Intel's Fab 68 in Dalian, China. The introduction of a leading-edge process, such as the P1272 14-nm FinFET process, is clearly fundamental to maintaining Leixlip as an Intel chip manufacturing site. A large sign was noticeable in communal area of Fab 24 that said: "Our chance to shine – 14-nm."




Eamonn Sinnott, general manager of Intel Ireland, discusses the history of the Leixlip wafer fab campus.

However, Intel Ireland is still conducting a $500 million refurbishment to upgrade the former Fab 14 to being capable of production on 300-mm wafers and to link it to Fab 24 with an "air-bridge." The bridge provides for one continuous clean environment extending from Fab 24 to what was Fab 14 allowing wafers to be moved between what were separate cleanrooms.

When the $500 million refurbishment of Fab 14 was announced in January 2011 it was described as a two-year project that would create about 200 long-term technical jobs once completed.

Meanwhile Fab 10, the first wafer fab constructed on the Leixlip campus back in 1991, has been decommissioned and stripped back to a bare shell. Fab 10 is mothballed for now although Intel staff said they are hopeful that the building can be recycled in a similar manner to the way in which the Fab 14 shell is being recycled.

Intel declined to say how many direct employees it has working on chip manufacture at Leixlip, at present.


Related links and articles:

London Calling: Intel's 14-nm process delay

Intel confirms Ireland for 14-nm silicon

Intel to invest $500 million in Irish fab
TAG:wafer fab Fab 24 Eamonn Sinnott Intel Ireland Intel Ireland Leixlip Dublin semiconductor process

翡翠市场未来发展扑朔迷离

翡翠市场未来发展扑朔迷离

近日，一条据称来自缅甸官方的消息在网上引起轩然大波，消息称，2013年起缅甸政府将禁止一切翡翠原石毛料出口，转而出口成品翡翠，把首都内比都打造成为可以替代阳美的翡翠贸易之都。

　　近日，一条据称来自缅甸官方的消息在网上引起轩然大波，消息称，2013年起缅甸政府将禁止一切翡翠原石毛料出口，转而出口成品翡翠，把首都内比都打造成为可以替代阳美的翡翠贸易之都。对于中国来缅甸经营的商人免费给土地使用权，从事翡翠雕刻的师傅一律2年免签。一石激起千层浪，不少翡翠商家、翠友及相关投资者顿感危机重重，担忧我国翡翠市场将遭遇重创。

　　消息不是空穴来风，但有待证实

　　近几年，缅甸政府不断发展翡翠加工业，从过去单纯的原石出口转向利润更高的半成品甚至成品出口。

　　“我觉得，缅甸出口加工翡翠将是一个现实。” 近几年我国翡翠原石进口的关税过高，导致大量原石在海关积压。拿一块要价1000万的翡翠原石来举例，要加收300多万的税，让一些靠借高利贷来炒原石的人不堪重负。近些年，关税以及外来资金的流入，扰乱了市场，翡翠就地加工其实非常合适。“大约十天前，我已经在广东得到了这个消息，虽然还没有看到正式发布，但是这个消息很可能是从源头那里流出来的。据我了解，已经有一些加工厂打算迁到缅甸了，很可能过完春节，明年三月份以后就搬去缅甸。我也准备派一个人去学缅甸语。”

　　缅甸出口成品翡翠，不容易实现

　　国家宝玉石专家认为，“翡翠文化，根在中国，石在异乡”，擅长雕琢高端翡翠、收藏翡翠、鉴赏翡翠的人群主要集中在中国大陆。翡翠的原料选取、设计制作、品评鉴赏到消费，整个链条都在中国内地。即使个别玉工迁移到缅甸，也很难支撑起缅甸的加工产业。而且缅甸政府想要发展翡翠加工业，需要缅甸政治稳定，市场完善，流通活跃，渠道畅通，目前缅甸国内政局不稳定，局部战争频繁，在缅甸国内形成具有翡翠文化的产业体系不容易实现。

　　“这可能是缅甸政府的一个美好愿望。”对于缅甸来讲，这样做确实可以带动就业，增加产品附加值，但要想形成一个繁荣的市场，不管是像揭阳还是瑞丽，都需要至少几十年。缅甸目前的加工水平很差，装置简单，工艺原始，规模较小，多以家庭作业为主，出口过来的一个打磨好的戒面，我们这边还要再进行改型。一旦缅甸的翡翠成品销售难以实现，资金上出现问题，这种出口模式是难以维持下去的。

　　翡翠市场未来发展尚存悬念

　　如果缅甸政府禁止翡翠原石毛料出口真的落实成政府政策，对我国翡翠市场的影响立竿见影。首先是国内市场原料少了，缅甸的翡翠加工业又是刚刚起步，一个产业至少需要三五年才能从无到有发展起来，到时候国内翡翠成品的货源断了，市场一定受影响。另外，此种政策一旦出台，国内的一些翡翠炒家一定会顺势炒作一把，进一步抬高翡翠的价格。

　　市场受不受影响，要看资源存量大小。近十年，由于中国经济的高速发展和中国内地翡翠市场的向好，使得中国在国际翡翠市场上有超强的购买力，缅甸人将大量的翡翠资源转给了中国人。现在，不论是收藏家、炒家、原料供应商，手上都不同程度地持有一定量的翡翠，缅甸国内市场的变动，恰恰为我国翡翠资源的消化创造了契机。“中低档翡翠国内存量较大，短期内价格不会有太大变动。”近5年在俄罗斯、南美陆续有翡翠矿源的发现，从见过的部分样品显示，有较高的商业价值。

　　目前缅甸的政治经济走势还有待观察，工业环境、基础设施等处于比较原始的状态，不足以迅速形成翡翠贸易中心。况且翡翠行家中仍囤有不少翡翠原料，可以维持翡翠资源在今后几年处于相对平稳状态。今年缅甸因国内国外的各种关系，已经取消了两次公盘，2013年缅甸的相关翡翠政策必将是翡翠业界关注的焦点。

TAG:

用暖色珠宝点亮严冬

用暖色珠宝点亮严冬

　　气温骤降，该是衣柜换季的时候了，别忘了也给自己的珠宝配饰换换季节。冷色调的首饰显然不再适合，挑选几件暖色的珠宝配饰作为冬季点睛品吧，热辣的红色，暖暖的金色都是不错的选择，别致一点，从视觉上，带给自己和他人汩汩暖意。

TAG:珠宝 暖色 红色 金色 用暖色珠宝点亮严冬

Foundries not dead, just evolving, says Globalfoundries CEO

Foundries not dead, just evolving, says Globalfoundries CEO

SAN FRANCISCO--The fabless/foundry model may have its issues, but it’s a long way from being dead, said Globalfoundries CEO Ajit Manocha, speaking at the International Electron Devices Meeting (IEDM) here this week (Dec. 11).

Manocha dismissed critics who claim the fabless model is on its way to extinction, claiming instead that the foundry model is seeing huge growth rates and continuing to outpace other chip industry segments.

Indeed, it is integrated device manufacturers (IDMs), Manocha countered, who should be wary of the future. The integrated model was, he asserted, is a dead end.

While Manocha admitted the impact of mobility had certainly put pressure on the foundry model, forcing his company to pick up the pace, the CEO said Globalfoundries is poised to move to the next round of process technology nodes, even as other big foundry players drop off.



TAG:fabs foundries fabless

Meeting Zuckerberg and Mr. EUV

Meeting Zuckerberg and Mr. EUV

Within 24 hours of each other, I had the chance to meet Facebook’s Mark Zuckerberg and the guy I think of as Mr. EUV. These two men in black, polar opposites on the electronics spectrum, each taught me something in our brief encounters.

I was invited to Facebook’s holiday reception for the media thanks to my interest in the Open Compute Project, Facebook’s effort to drive industry standards for the gear that goes into their mega data centers. So I was delighted to see Frank Frankovsky there, the guy who drives the Open Compute effort.

Frankovsky made a guest appearance at the recent Intel press conference launching its Centerton SoC. The Atom-based chip is cool and Facebook plans to test it, but it lacks the umph for use in Facebook’s high volume Web tier which demands 8 to 16 cores running at 2.5 GHz or better, he said. Intel’s follow-on, the Avoton chip coming in 2013, has a better shot, he said.

The Facebook director has plenty of ARM SoC makers knocking on his door to find out exactly what he would like them to put in their next-generation chips. So Frankovsky says he feels no need to start his own SoC design project.

Facebook has some “big news” for the Open Compute Summit coming in January, Frankovsky said. I am guessing it is either a new mega data center such as eBay joining the project or an initiative in a new area like switching—after all switch guru and Arista founder Andy Bechtolsheim is on the Open Compute board.

So I figured I had my fill of networking and was just tucking into a little sushi when I notice Mark Zuckerberg had arrived in his signature black hoodie.
Next: The Zuckerberg files
TAG:Data Centers Social Networks Extreme Ultraviolet Zuckerberg Facebook EUV Lithography IEDM Imec

Foundries not dead, just evolving says Globalfoundries CEO

Foundries not dead, just evolving says Globalfoundries CEO

SAN FRANCISCO--The fabless/foundry model may have its issues, but it’s a long way from being dead, said Globalfoundries CEO Ajit Manocha, speaking at the International Electron Devices Meeting (IEDM) here this week (Dec. 11).

Manocha dismissed various industry observers who have claimed the fabless model is on its way to extinction, claiming instead, the foundry model was seeing huge growth rates and continuing to outpace the semiconductor industry.

Indeed, it was integrated device manufacturers (IDMs), said Manocha, who should be wary of the future, because aside from a small number of anomalies with the financial wherewithal or stubbornness to continue along the path, the integrated model was, in his opinion, a dead end.

While Manocha admitted the impact of mobility had certainly put pressure on the foundry model, forcing his company to pick up the pace, the CEO said he still firmly believed his firm had what it took to make it through to the next round of ever lower nodes, even as other big foundry players drop off.



“Only four players have capabilities to offer leading edge technologies beyond 28nm,” he said, citing, Intel, Samsung, TSMC and Globalfoundries. This, he said, made the foundry market opportunity all the more compelling and concentrated at the leading edge, with a compound annual growth rate (CAGR) of some 37 percent in the next three years. In terms of monetary value, Manocha said the leading edge now represented a $27.5 billion opportunity, something Globalfoundries doesn’t intend to relinquish in a hurry.



That’s not to say there weren’t still challenges to keep Manocha awake at night. The Globalfoundries chief said potential problems could be divided twofold into technical and economic challenges, with each presenting difficulties still needing to be overcome.

On the technical challenge side, Manocha spoke of the hardships of achieving the required power density for the right battery life, at a low cost, while ensuring the technology remained reliable and the interconnects held up. Retaining talent and being able to collaborate with clients at the earliest stages was also cited as a technical difficulty, but ones Manocha said Globalfoundries was committed to overcoming.



On the economic side, Manocha spoke of the trials caused by cyclicality and capacity, design and manufacturing costs, the geographic risks impacting supply, IP and competition issues.

Click for next page >>
Next: Moving to Foundry 2.0
TAG:fabs foundries fabless

Intel's FinFETs approach draws fire from rivals

Intel's FinFETs approach draws fire from rivals

SAN FRANCISCO – A panel of experts debated the future of semiconductor technology amid an array of new structures and materials, some trashing the FinFETs popularized by Intel. They made it clear there is no single road forward but rather a set of uncertain paths, each with its trade-offs.

“It’s clear planar silicon as we know it ends at about the 20-nm node, then there will be a race to different architectures and materials or combinations of both,” said Suresh Venkatesan, senior vice president of technology development at Globalfoundries, moderating an panel at the International Electron Devices Meeting (IEDM).

An IBM expert challenged that statement, showing a 10-nm planar process.

Panelists argued for an assortment of options including FinFETS, germanium, III-V materials, tunnel FETs, nanowires and fully depleted silicon-on-insulator. All sides agreed just what defines a new node is increasingly unclear.

“Any time we talk about new nodes, we should wash our mouths out with soap,” said Scott Thompson, chief technologist of startup SuVolta and a former Intel fellow. Engineers ignore traditional metrics, he added. “Intel’s 22 nm node is really 26 nm, so if Intel does new math, so will we."

“The next node after 14 nm will be some small number, but there’s no real pitch scaling,” Thompson added. “Pitch scaling will slow, but we will still have smaller number nodes anyway,” he said (see below).



Click on image to enlarge.
Next: Fur flies over FinFETs
TAG:International Electron Devices Meeting III V Materials Tunnel FETs FinFETs IEDM Germanium Nanowires SOI

London Calling: Could gate-switched FDSOI win?

London Calling: Could gate-switched FDSOI win?

The contentious issue of gate-first or gate-last in front-end of line (FEOL) chip manufacturing is raising its ugly head again; but this time in with regard to the fully-depleted silicon on insulator (FDSOI) process.

Some readers may remember that gate-first high-k metal gate technology was developed and touted by IBM's circle of chip manufacturing partners for the 32/28-nm bulk CMOS node. This was a contrast to the gate-last position taken by Intel, which of course went on to introduce the FinFET or tri-gate transistor at nominal 28-nm and 22-nm nodes. But IBM's bulk CMOS technology partners revealed that having gone gate-first at 28-nm they would move to gate-last at the 20-nm node.

Professor Asen Asenov, of Glasgow University and CEO of TCAD company Gold Standard Simulations Ltd. (GSS), has used its TCAD simulator to investigate the statistical variability in 32/28-nm FDSOI in comparison to equivalent bulk MOSFETs and studied the difference between metal-gate-first and metal-gate-last flavors of the technology. "Metal-gate-first FDSOI will be very good but metal-gate-last could be spectacular," said Professor Asenov.

But unfortunately nobody makes metal-gate-last. STMicroelectronics NV has started to offer gate-first FDSOI but so far doesn't seem to have much traction for the technology.

"Bulk CMOS has a problem of high variability; at 28-nm it is OK but at 22/20-nm it becomes serious. SRAM is most critical in terms of variability and SRAM is pervasive in SoC," Professor Asenov told EE Times. One of the tricks to make bulk CMOS work at 20-nm is to reduce the scaling of SRAM blocks but there is still a lot of leakage making 20-nm bulk CMOS power hungry, he added.

According to Professor Asenov's simulations FDSOI has advantages over both FinFET and bulk CMOS processes at the 28-nm node and beyond. This is because the reduced variability afforded by gate-last FDSOI means operating voltage can be taken lower before SRAM cells stop working. This opens up the range of voltage and frequency scaling that is possible and as power consumption is proportional to the square of voltage this makes a big difference in low voltage modes where application processors spend most of their time.

"The breaking news here is that if you can develop a metal-gate-last 28-nm FDSOI technology you will be able to achieve an astonishing SRAM supply voltage, in the range of 0.5 to 0.6 volts," said Asenov, in a statement. "Equivalent bulk at 28-nm requires approximately 0.9-V to secure the reliable operation of large SRAM arrays. Metal-gate-first FDSOI reduces the minimal SRAM supply voltage below 0.7-V and metal-gate-last FDSOI at 28-nm can reduce Vcmin even further to below 0.5-V."

That's the good news for the FDSOI camp. The bad news is that Professor Asenov reckons that they have still got the manufacturing process the wrong way round. STMicroelectronics' gate-first 28-nm FDSOI does match the gate-first bulk CMOS at 28-nm which makes for an easier transfer of libraries and intellectual property but is not the optimum configuration, according to Professor Asenov.

"I believe FDSOI is a very good candidate for low power but very few designs are being made at 28-nm. TSMC or Samsung could get a huge advantage by introducing metal-gate-last FDSOI, probably much better than FinFET at the same geometry," Professor Asenov said.


Related links and articles:

Professor Asenov's blog

www.goldstandardsimulations.com

News articles:

IMEC reports on gate-last HKMG options

ST opens up FDSOI with GlobalFoundries

FDSOI roadmap renames next node as 14-nm

CEA-Leti claims ultra-low variability in FDSOI devices at 22-nm

Technical paper

Considerations for bulk CMOS to FDSOI design porting



TAG:Peter Clarke London Calling Asen Asenov FDSOI semiconductor process manufacturing

Device manufacturers' 'Holy Trinity'

Device manufacturers' 'Holy Trinity'

It's tough being a device manufacturer in today's marketplace.

The global market has recently seen increased competition from new players that has had a commoditizing effect across the spectrum - from medical devices and telecommunications equipment to oil and gas machinery and building automation. Complex supply chains and rising commodity, fuel and transportation prices are driving up manufacturing costs and margins down. Today’s rapidly evolving markets and changing customer needs require a heightened flexibility and nimbleness that most old-line manufacturers simply don't have.

While many device manufacturers are collapsing under the pressure, some are succeeding - exceptionally. The new winners in the global economy enjoy tremendous profitability, high margins and virtually infinite product customization capabilities. Their strategy represents the future of manufacturing.

Their formula for success should be copied by all manufacturers seeking to remain competitive – it could be referred to as a Holy Trinity. The strategy lies in the ability to become a solutions provider. The way to do this is by going intelligent.

The formula for intelligence is as follows: App-enabled Hardware + Flexible Licensing = Intelligent Device

As an example of how this works, look no further than Apple and the iPhone. Rather than manufacturing hundreds of different iPhone models, Apple only needs to manufacturer two or three. Built into these models are all iPhone functions and features: GPS, camera, light, voice, data.

The iPhone is an app-enabled hardware solution that allows the customer to download software to address particular needs. The functions and features on the device that get turned on and off – in different combinations, are defined by the app. As a result, the iPhone is personalized to the exact needs and specifications of the customer - accomplished almost entirely via the apps. This solution is almost indefinitely customizable, yet Apple only has to produce a few models (minimizing manufacturing costs).

Additionally, the functionality can be altered, enhanced and improved in the same amount of time it takes to download a new app.
Next: The Apple model
TAG:Flexera Software Vincent Smyth Holy Trinity Manufacturing

FDSOI roadmap renames next node as 14-nm

FDSOI roadmap renames next node as 14-nm

LONDON – Documents presented at the fully depleted silicon on insulator (FDSOI) workshop in San Francisco this week show that the FDSOI roadmap now omits a 20-nm and goes straight to 14-nm and then on to 10-nm.

A summary slide from Horacio Mendez, executive director of the SOI Consortium, showed the jump with the comment that 14-nm FDSOI would be offered at the same time as Intel's 14-nm FinFET and would show the same performance characteristics but realizable at much lower cost. A presentation by Joel Hartmann, executive vice president of front-end process for STMicroelectronics, at the same meeting, organized by the SOI Consortium, also shows the move from 28-nm FDSOI, a process that is has started to ship in the second-half of 2012, on to 14-nm FDSOI and then 10-nm FDSOI.

Previously ST has spoken of the 28-nm FDSOI process prototyping in July 2012 followed by a 20-nm FDSOI process prototyping in 3Q13.

The implication is that parties interested in the FDSOI roadmap are renaming what was the 20-nm node so they can be seen to be at an equivalent node to Intel 14-nm FinFET process and FinFET processes from foundries such as Taiwan Semiconductor Manufacturing Co. Ltd. and Globalfoundries.

Hartmann's presentation provided the most recent results measured for the 28-nm FDSOI process made with multi-core ModAp NovaThor processor from ST-Ericsson and made extensive claims for the superiority of 28-nm ST's gate-first FDSOI manufacturing process in comparison with 28-nm bulk CMOS process in terms of ease of manufacture lower power consumption and higher performance.

Mendez shows the FDSOI roadmap now includes a 10-nm process to be offered in 2016, which will also be the point at which the FDSOI roadmap would introduce the option of FinFET over SOI.


Click on image to enlarge.
Fully depleted vision for SoCs through 10-nm. Source: SOI Consortium


Related links and articles:

www.soiconsortium.org

News articles:

28-nm FDSOI is production ready, says ST

ST voices new strategy, recommits to fully depleted SOI

SuVolta reports 65nm parameter results at IEDM

Intel's 22-nm tri-gate SoC process



TAG:SOI Consortium STMicroelectronics semiconductor

IBM details 3-D server chip stacks

IBM details 3-D server chip stacks

SAN JOSE, Calif. – IBM will provide a deeper look into its work on 3-D chip stacks at the International Electron Devices Meeting (IEDM) here, detailing work on stacks of 45-nm server processors with memory and transceivers.

Big Blue has long been expected to be among the early users of 3-D stacking to pair its server CPUs with memories for performance and power advantages. It has been collaborating with Micron on the Hybrid Memory Cube, a memory stack for just such applications.

“As scaling saturates, and lithography sputters to a grinding halt, these orthogonal scaling techniques will assume even more importance and continue to keep Moore’s ‘law’ alive,” wrote Subraman S. Iyer, a senior IBM technologist in the IEDM paper to be presented Wednesday (Dec. 12).

The paper shows IBM’s road map extending from embedded DRAM to various 3-D stacks with and without interposers using face-to-face and back-to-back stacks. In a separate paper, IBM disclosed the top two layers of metal in its new 22-nm process are optimized for use with through silicon vias needed for 3-D stacks.

“Embedded DRAM, 3D stacking, interposers and wafer-to-wafer integration are intrinsic to this [IBM] roadmap,” Iyer’s paper said.

Click on image to enlarge.Related stories:

IEDM goes deep on 3-D circuits

IBM, Intel face-off in 22 nm process at IEDM

Moore’s Law predicted to hit big bump at 14 nm
Next: 2 Terabits/s throughput
TAG:Through Silicon Vias 3 D stacks Chip Stacking 3 D IBM TSVs IEDM Stacking Interposers Iyer

MediaTek targets Qualcomm with quad-core/modem SoC

MediaTek targets Qualcomm with quad-core/modem SoC

NEW YORK – MediaTek, the world’s fastest growing smartphone chip supplier, has this week begun sampling what the company calls “the industry’s first commercial quad-core smartphone chips, integrated with multimode modem.”

Others are already shipping quad-core apps processors, but none has introduced an apps processor integrated with a modem in a single chip, claimed Finbarr Moynihan, MediaTek’s general manager for business development.

MediaTek's quad‐core Cortex‐A7 SoC, dubbed MT6589, is being positioned to compete head-to-head with Qualcomm, which announced last week two new quad-core chips, similarly integrated with a modem that works with UMTS, CDMA and TD-SCDMA.

Both are based on ARM’s Cortex A7 cores.

The difference is that “we are sampling now, and the chips are ready for mass production in the first quarter of 2013,” Moynihan said. “We have a customer shipping in January handsets with MediaTek’s quad-core chip inside.” Qualcomm’s quad-core chips will start sampling in the second quarter of next year, with volume production scheduled for the second half of 2013.

MediaTek's SoC, fabricated using a 28-nm process, integrates its multi‐mode UMTS Rel. 8/HSPA+/TD‐SCDMA modem, a quad‐core Cortex‐A7 CPU subsystem from ARM and a PowerVR Series5XT GPU from Imagination Technologies.

10-fold growth

Drawing a sharp distinction between mobile chip vendors who have seen the market shrink due to the dominance by smartphone chip giants like Qualcomm and Samsung, MediaTek said its smartphone chip shipments increased more than ten-fold this year, from 10 million units in 2011 to 110 million units.

Key to this success was MediaTek’s mid- to entry-level smartphone chip platform based on its single-core Cortex A-based MT6577 running at 1 GHz and a dual-core, 1-GHz Cortex A9-based MT6577. That platform was primarily designed for the under-$190 smartphone market, Moynihan said.

MediaTek said it plans to move up the value chain to tackle the market for premium- to high-level smartphones everywhere but the U.S.

In the first half of 2012, Strategy Analytics ranked MediaTek second (with a 12.8 percent share of revenues) in the global cellular baseband processor market that includes2G, 3G and LTE. While MediaTek’s strength in the feature phone market is well known, MediaTek made significant progress with the “help of its strong 3G smartphone processor shipments,” according to the market researcher.

MediaTek’s quad-core SoC adds HSPA+ and TD-SCDMA to the company’s established 3G/HSPA modem. This is “the first platform for HSPA+, supporting Dual-SIM" so users don't miss calls, Moynihan said.

The dual SIM card phone played a critical role in the proliferation of feature phones in Asia since they enable the use of two services on a single phone. As data usage increases, the importance of the dual-SIM feature has become even more important. "A user could be surfing the Web on a 3G SIM card and simultaneously receive a call on a 2G SIM card, for example,” said Moynihan. Handset vendors, however, would still need to add an extra radio and transceiver to make this dual-active mode work.
Next: Why quad-core?
TAG:Quad Cores Appls Processor MediaTek Qualcomm

Intel leapfrogs ARM (for now) with Atom server SoC

Intel leapfrogs ARM (for now) with Atom server SoC

SAN JOSE, Calif. – Leaping ahead of a growing onslaught of ARM server SoCs, Intel Corp. rolled out its dual-core, 64-bit Atom enterprise SoC, claiming 20 design wins in microservers, comms and storage. It also said it will pack an Ethernet fabric on to its next-generation, Avoton, a 22-nm chip shipping in 2013 that is expected to use out-of-order cores for greater performance.

The move puts Intel well ahead of a half-dozen ARM-based competitors, none of which will have 64-bit chips until sometime in 2013. Even those who have working 32-bit chips now have far fewer design wins.

Intel claims the new S1200 chip, dubbed Centerton, displaces the PowerPC in a comms control plane design and ARM in a storage system. The design wins span a range of top-tier OEMs to little known names, including Accusys, CETC, Dell, Hewlett-Packard, Huawei, Inspur, Microsan, Qsan, Quanta, Supermicro and Wiwynn.

The battle is only just begun. ARM server SoC backers now include Advanced Micro Devices, Applied Micro, Cavium, Calxeda, Nvidia and Samsung. In addition, Freescale, LSI and Cavium are moving toward ARM cores for server and storage SoCs, joining Texas Instruments.

Many in the ARM camp have committed to 64-bit products which likely won't enter volume production until 2014. Intel vowed to provide annual upgrades of its new Atom enterprise SoC line, including a 14-nm part to come as early as 2014.

“This doesn’t have a big impact on the ARM 64-bit players because they have developed their road maps with Intel’s Centerton and Avoton in mind,” said Patrick Moorhead, principal of Moor Insights and Strategy (Austin, Texas). The new Atom chip, “will not be lowest power or densest solution compared with ARM-based solutions from Calxeda, Applied Micro or AMD,” he added.
Next: HP, Intel, Facebook onboard
TAG:Server SoCs Centerton Intel ARM Servers HP Facebook Avoton S1200

Huawei, spurned by U.S., expands in Europe

Huawei, spurned by U.S., expands in Europe

SAN FRANCISCO—Chinese telecom infrastructure manufacturer Huawei Technologies has set its sights on expanding its European base after security concerns in the U.S. slowed the company’s North American progress.

Huawei said Monday (Dec. 10) that it will double its European workforce, employing more than 14,000 workers over the next three to five years, providing jobs in areas recently hard hit by tech layoffs.

In Finland, where Huawei said it intends to open and invest some 70 million euros ($91 million) in an R&D center for new smartphones, snapping up employees laid off by local firm Nokia. The center would be Huawei’s eleventh in the region, with a staff of around 100 people.

By consolidating its foothold in Europe, Huawei is also muscling in on territory formerly belonging to local infrastructure players like Ericsson, from whom the Chinese company just won over a service deal with large U.K. mobile provider, 3, owned by Hutchison Whampoa.

By making smartphone devices as well as providing the infrastructure, Huawei is thought to have a unique value proposition. By delivering devices running Android and soon Microsoft’s Windows 8, Huawei can put even more pressure on European incumbents like Nokia. Indeed, Huawei’s device business unit brought in 22 percent of the firm’s revenue last year.

While the move seems logical, it has also come as a result of pressure from the U.S. government, where congress recently released a report stating that the firm’s infrastructure posed an espionage risk. It’s not the first time Huawei has been accused of spy games, either. Australia banned the firm from participating in a national tender to build the country’s high-speed broadband network over “security concerns.”

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U.S. warns telcos not to buy from China
Citing security concerns, India slows Huawei expansion plans
Yoshida in China: Huawei MIA in Windows Phone 8
Focus on Chip Engineering Rewrites Huawei's Story


TAG:telecom huawei espionage

Renesas eyes foreign CEO, nominations welcome

Renesas eyes foreign CEO, nominations welcome

NEW YORK – There’s nothing surprising about Japan Inc. going out of its way to bail out Renesas Electronics. The obvious objective is to maintain a steady flow of Renesas chips into domestic products, especially Toyota and Nissan automobiles.

Surprising, however, are rumors that the new owners of Renesas are looking for a foreign executive to head up the company.

Under the deal announced Monday (Dec. 10), the Innovation Network Corp. of Japan (INCJ), a public-private partnership, will pay 138 billion yen ($167.5 million) to acquire a 69 percent stake in Renesas. Eight major Renesas customers, including Toyota, Nissan, Canon and Panasonic, will pay almost 12 billion yen ($14.6 million) for a 6 percent stake.

That means the chip maker's former majority shareholders – NEC, Hitachi and Mitsubishi – will see their share drop from 90 to 23 percent. The trio joined forces to form Renesas by combining their loss-making chip operations, but are showing no interest in a majority stake in Renesas. The three companies agreed to accept some laid-off Renesas employees, and to provide loans for restructuring. But it’s clear. They aren’t committed to doing anything beyond that.


(Source: Nikkei.com)
TAG:Renesas Bailout CEO

Toshiba claims MRAM can replace SRAM

Toshiba claims MRAM can replace SRAM

LONDON - Toshiba has developed a prototype spin transfer torque magnetoresistive random access memory (STT-MRAM) that it expects to be used to replace SRAM in cache memory for mobile processors within smartphones and tablet computers.

The STT-MRAM structure, the subject of a paper at IEDM 2012, taking place this week, has the lowest power consumption yet reported, and is about one-tenth that of prior reported prototypes, Toshiba said. Because of this Toshiba reckons it is the first MRAM able to compete with SRAM for cache applications and the company said it intends to accelerate R&D to that end.

The improved structure is based on perpendicular magnetization. This can be reversed at lower energy than in-plane magnetization, making it possible to program data at lower currents and fabricate smaller memory cells. The latest work by Toshiba takes the element miniaturization below 30-nm. The memory circuit has no leakage current both in operation and in standby, Toshiba said.




Toshiba STT-MRAM structure with vertical magnetization and 30-nm memory size.


The STT-MRAM structure provides an MRAM that can be of lower power consumption than its SRAM equivalent. Toshiba has also written a simulation of how such an STT-MRAM would perform as cache memory in a mobile processor application and recorded a 66 percent reduction in power consumption for standard operating functions.

The memory is the result of the "Normally-off Computing" project funded by Japan's NEDO (New Energy and Industrial Technology Development Organization). Toshiba is presenting three papers on the STT-MRAM at IEDM.


Related links and articles:

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Everspin samples 64-Mb spin-torque MRAM

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TAG:Smartphone tablet computer STT MRAM MRAM SRAM Toshiba semiconductor IEDM

28-nm FDSOI is production ready, says ST

28-nm FDSOI is production ready, says ST

LONDON – STMicroelectronics has announced that its 28-nm fully depleted silicon-on-insulator (FDSOI) is available for pre-production from its Crolles 300-mm wafer facility.

The FDSOI planar process is claimed to have advantages over other manufacturing process variants, such as bulk planar CMOS and FinFET CMOS in terms of trade-offs between performance, power consumption and manufacturability. ST was due to begin prototyping 28-nm FDSOI in July 2012 with 20-nm FDSOI due to be ready for prototyping in 3Q13. In addition, ST has a licensing agreement with foundry Globalfoundries Inc. (Milpitas, Calif.) to be a FDSOI production and to open up the process to more customers.

ST's announcement coincides with a workshop on FDSOI being held in San Francisco alongside the International Electron Devices Meeting.

ST's FDSOI technology platform includes standard cells, memory generators, I/O cells and specific circuit blocks for analog, mixed-signal and high-speed interfaces licensable as intellectual property. The technology has been selected by ST-Ericsson for use in future mobile equipment platforms.

"By bringing FDSOI technology to manufacturing readiness, ST is again positioning itself as an innovator and leader in semiconductor technology development and manufacturing," said Jean-Marc Chery, chief technology and manufacturing officer of STMicroelectronics, in a statement. "Post-processing wafer testing has allowed us to prove the significant performance and power advantages of FDSOI over conventional technologies, building a cost-effective industrial solution that is available from the 28-nm node."

FDSOI can operate at low voltage with "superior energy efficiency" compared with bulk CMOS, ST claimed.

Chery said that ST has performed measurements on a multi-core subsystem in an ST-Ericsson NovaThor IC that combines baseband modem and application processor. The subsystem is capable of operating at 800-MHz clock frequency at 0.6 volts but can also operate at 2.5-GHz clock frequency at higher voltage, ST said. This demonstrates an extended dynamic voltage and frequency scaling (DVFS) regime.

FDSOI enables production of highly energy-efficient devices, with the use of dynamic body-bias allowing an instant switch to high-performance mode when needed and a return to reduced-leakage state for the rest of the time.


Related links and articles:

www.soiconsortium.org

News articles:

ST remains commited to FDSOI

ST to exit ST-Ericsson in 2013

ST opens up 28-nm, 20-nm FDSOI with GlobalFoundries


TAG:FDSOI SOI ST process semiconductor manufacturing

Micron reportedly preps Israel job cuts

Micron reportedly preps Israel job cuts

LONDON – Memory chip maker Micron Technology Inc. (Boise, Idaho) is preparing to lay off about one third of its workforce at its wafer fab in Israel, according to local news reports.

The job cuts will be at Micron's flash memory manufacturing plant at Kiryat Gat, Israel, and are set to include about 500 out of the 1,300 people employed there, according to the Calcalist newspaper. They will take place during 2013, the newspaper said.

Micron job cuts would be the latest in a wave of job cuts in hardware sector of the electronics industry that has hit Israel since October, according to reports in the Calcalist and Globes newspapers. Orbotek and Freescale Semiconductor have both made large job cuts recently the reports said.

Micron's Kiryat Gat fab was originally built by Intel as its Fab 18 before being transferred to Numonyx NV, a joint venture company formed in 2008 by Intel, STMicroelectronics and Francisco Partners to make flash memory ICs. Numonyx and the fab was acquired by Micron in 2010.

In September 2012, Micron announced it had made a net loss of $1.03 billion on net sales of $8.2 billion for the 2012 fiscal year. For the previous fiscal year Micron reported a net income of $167 million on net sales of $8.8 million.

Micron was contacted but did not comment on the reports by the time this story was posted.


Related links and articles:

www.micron.com

Calcalist article

EE Times news articles:

Freescale's i.MX 7 canned as firm refocuses

Numonyx takes on staff as it cuts contractors

Intel chooses Ireland over Israel

TAG:Kiryat Gat wafer fab Micron DRAM flash memory semiconductor jobs

Moore’s Law seen hitting big bump at 14 nm

Moore’s Law seen hitting big bump at 14 nm

SAN FRANCISCO – Chips made at the 14-nm procees node may deliver as little as half the typical 30 percent performance increase—and still carry a hefty cost premium--due to the lack of next-generation lithography needed to make them efficiently, according to experts speaking at the International Electron Devices Meeting (IEDM) here on Monday (Dec. 10).

Chip makers must choose lithography options now for 14-nm node, two generation away from the 28-nm node in wide production for today’s smallest devices. But it will not be until 2014 that extreme ultraviolet (EUV) lithography tools will be available for limited commercial use, said Luc van den Hove, chief executive of the IMEC research center in Belgium, speaking to EE Times after a keynote talk here.

The cost of 14-nm wafers made with today’s 193-nm immersion lithography systems will be more than 90 percent greater than the cost of today’s 28-nm wafers. EUV would shave that increase to just under 60 percent, van den Hove estimated in his talk (see chart below).


Click on image to enlarge.
The cost comes from the need to make as many as three exposures with today’s systems compared to just one with EUV. “The triple patterning is too complex so you will have to relax design rules or the chips will not yield,” said Kurt Ronse, an IMEC lithography specialist.

As a result, 14-nm chips likely will deliver about 15 to 20 percent performance boosts over the prior generation, rather than the typical 30 percent boost, estimated Ronse.

“It is likely some design rules at 14 nm will have to be relaxed somewhat,” said van den Hove in his keynote. “I believe the time to decide lithography options for 14 nm is basically now, and its clear EUV is not ready for the challenge,” he added, in response to a question.

“There is a tremendous effort to solve the [EUV] problems,” said van den Hove. “We believe the problems are not fundamental, they are engineering but it will require time."
Next: Test driving EUV
TAG:International Electron Devices Meeting Moore’s Law 14 Nm IEDM EUV Lithography Imec

Suede Handbag How you can Get Good Treatment of It Womens Leather Handbag On Sale

A suede purse would be the ideal style accessory at this time and it’s grow to be a dream possession of every fashion conscious girl. However, considering that the suede leather is developed through the reduced layer of the lambskin leather, it tends t get dirty incredibly quickly mainly because it absorbs dust and moisture at a quick amount. To avoid these problems using your suede purses and extend their lifestyle, you will need to comply with some simple ways to be sure which you are taking good care of them. With correct standard treatment, you’ll be capable to implement your favored suede handbags for a lot of seasons to return.

You can require several essential things to just take treatment of your favorite suede purse. To scrub and defend your purses from grime and moisture, you might demand a suede brush, suede protector, suede cleaner along with a really hard rubber eraser. It’s best to get a suede cleaner and drinking water repellent together with your suede handbag to make sure excellent care within your new purse from the really beginning. You need to spray two layers in the suede protector on your purse to make certain appropriate protection. It is actually recommended that you total this procedure within the external and from the absence of potent wind, in order that your suede purse easily absorbs the protector liquid.

For that day-to-day treatment within your handbag, you may brush it gently when using the suede brush to keep absent dirt together with other particulate matter from your surface area from the bag. Having said that, do remember to brush in one route only. Multi-directional brush strokes will harm the texture of your suede handbag. If possible, study the instruction booklet that every manufacturer provides with their suede purses, which has recommendations regarding the appropriate brushing method to maintain your handbag’s affliction.

By far the most important factor you must contemplate whilst taking care of suede handbags, is you will need to maintain them dry. Moisture harms the texture and softness of suede, harmful your purse substantially. If you want to wash stains off your suede purse, you are able to utilize the tough rubber eraser to rub off the stain off its surface area. Beneath no conditions, should you use soap on your own handbag. Often remember to stuff paper in it whenever you choose to continue to keep it in storage to ensure it is actually equipped to keep its genuine form. These are generally the very few very simple ways, which it’s essential to comply with to get very good treatment of your suede purse.

Suede Handbag How you can Get Good Treatment of It Womens Leather Handbag On Sale

TAG:handbag suede treatment

IBM, Intel face off at 22 nm

IBM, Intel face off at 22 nm

SAN FRANCISCO – Intel and IBM went head-to-head with their latest 22-nm technologies in back-to-back papers at the International Electron Devices Meeting (IEDM) here Monday (Dec. 10). Separately, a top Intel fab executive commented on increasing wafer costs and the company’s foundry business.

IBM said it is prototyping server processors in a new 3-D ready, 22-nm process technology it hopes will deliver 25 to 35 percent boosts over its 32-nm node. Intel retains an edge with several 22-nm chips already in volume production, and disclosure at IEDM of a variant of the process for SoCs for a wide range of applications.

The Intel paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” Mark Bohr, head of Intel’s process technology development group, said in a brief interview. The process is geared for a much wider array of designs than that of IBM, he added.

Bohr said Intel’s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28-nm planar process. The addition of FinFET adds only 3 percent to the cost of the process. Its use of 80-nm minimum feature sizes can be made with a single pass of 193-nm lithography tools, making it cost effective.

Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

Separately, Bohr said Intel does have a growing foundry business that may include some higher volume applications than its current announced customers like FPGA startup Achronix. However, “we don’t intend to be in the general-purpose foundry business…[and] I don’t think the [foundry] volumes ever will be huge” for Intel, he said.
Next: Intel’s 22-nm SoC process
TAG:International Electron Devices Meeting Process Technology 22 Nm Embedded DRAM 3 D Intel IBM IEDM

IBM, Intel face off in 22 nm process at IEDM

IBM, Intel face off in 22 nm process at IEDM

SAN FRANCISCO – Intel and IBM went head-to-head with their latest 22 nm technologies in back-to-back papers at the International Electron Devices Meeting (IEDM) here. Separately, a top Intel fab executive commented on increasing wafer costs and the company’s foundry business.

IBM said it is prototyping server processors in a new 3-D ready, 22 nm process technology it hopes will deliver 25 to 35 percent boosts over its 32 nm node. Intel retains an edge with several 22 nm chips already in volume production, and disclosure at IEDM of a variant of the process for system-on-chips for a wide range of applications.

The Intel paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” said Mark Bohr, head of Intel’s process technology development group in a brief discussion with EE Times before the session. The process is geared for a much wider array of designs than that of IBM, he said.

Bohr said Intel’s 22 nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28 nm planar process. The addition of FinFET adds only three percent to the cost of the process. Its use of 80 nm minimum feature sizes can be made with a single pass of 193 nm lithography tools, making it cost effective, he added.

Projections from an Imec keynote that 14 nm wafers will be 90 percent more expensive than 28 nm parts due to the lack of EUV lithography are inaccurate, Bohr said. The cost increase for 14 nm wafers at Intel “is nowhere near that,” he said.

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” he told EE Times.

Separately Bohr said Intel does have a growing foundry business that may include some higher volume applications than its current announced customers such as FPGA startup Achronix. However, “we don’t intend to be in the general-purpose foundry business…[and] I don’t think the [foundry] volumes ever will be huge” for Intel, he said.

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Intel describes 22nm SoC process, not chips

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Next: Inside Intel’s 22 nm SoC process
TAG:International Electron Devices Meeting Process Technology 22 Nm Embedded DRAM 3 D Intel IBM IEDM

MIT integrates InGaAs in 22-nm design flow

MIT integrates InGaAs in 22-nm design flow

PORTLAND, Ore. -- Integrating III-V transistors into 22-nm design flows may soon be possible, according to the Massachusetts Institute of Technology (MIT) researches who demonstrated indium-gallium arsenide (InGaAs) transistors at the International Electron Devices Meeting (IEDM) this week in San Francisco.

Since 2009, Intel has been tweaking high-k metal gate stacks for III-V transistor channels while Toyohashi University of Technology claimed last year to have solved the lattice mismatch in depositing gallium arsenide on silicon substrates.

MIT demonstrated an indium gallium arsenide transistor that it claims can be shrunk to smaller dimensions than silicon. Built by MIT’s Microsystems Technology Laboratories, the researchers claim their 22-nm demonstration transistor show that InGaAs is a promising candidate to replace silicon at advanced technology nodes.

Employing the same MOSFET architecture as conventional CMOS transistors, the researchers used self-aligning techniques to fabricate the nanoscale gate. Using molecular beam epitaxy to deposit the channel, molybdenum was then deposited using e-beam lithography to form the source and drain electrodes. The middle gate was then etched with oxide deposited on top after which evaporated molybdenum was fired at the surface.

"With a combination of etching and deposition we can get the gate nestled [between the source and drain electrodes] with tiny gaps around it," MIT said.

The MIT is next aiming to improve the electrical performance of their InGaAs transistor by optimizing the stack to reduce resistance. The team's ultimate goal is to produce III-V transistors that are faster than silicon and have gate lengths as short as 10 nm.

Related stories:

Intel tweaks high-k stack to get GaAs on silicon

Researchers report solid-state quantum leaps



TAG:International Electron Devices Meeting IEDM Semiconductors

龙凤玉佩品相最多变

龙凤玉佩品相最多变

如果有人问：在中国历代吉祥佩饰中，哪一种最常见、品相最多变、吉祥含义最丰富？那么可以毫不犹豫地给出答案：那就是龙凤玉佩。 　　如果有人问：在中国历代吉祥佩饰中，哪一种最常见、品相最多变、吉祥含义最丰富？那么可以毫不犹豫地给出答案：那就是龙凤玉佩。

　　龙是中华民族最古老的图腾之一，是国家、帝王以及男性阳刚的象征。龙的形象集中了虎、蛇、鹰、鱼、牛等九种动物的特征，能适应陆上、水上、天上等各种环境，在中国人心目中，龙几乎无所不能，因而把龙视为四灵(龙、凤、麒麟、龟)之首。凤鸟的起源也很早，它是女性的化身，是阴柔美的代表。凤鸟是由鸡的头、鸳鸯的翅、孔雀的尾、仙鹤的脚组合而成的神鸟，古人把它视为百禽之王。认为它具备仁、义、德、顺、信五德，象征幸福、和美、团圆。

　　龙与凤阴阳相对，其组合既代表阴阳和谐，又代表男女相生相合，故有龙凤呈祥、龙飞凤舞之说。因此龙凤佩最受人们喜爱，自然成为中国吉祥含义最丰富的佩饰。

　　龙凤玉佩可细分为龙形佩、凤鸟佩、龙凤组合佩、夔龙佩、夔凤佩等几种。而最早的龙凤玉器造型并不具备后人所描述的形态，其形象是在不断演变的过程中逐渐完善的。五千多年前的红山文化玉龙主要有两种形态：一是猪首龙形；二是“C”字形龙。红山玉凤鸟的形态为一侧面展翅的凤鸟。商代的龙凤玉器开始雕琢纹饰，西周、春秋时期的玉龙凤多为浮雕，纹饰更加繁密，更富装饰性。战国、汉代的龙凤玉佩风格大变，形态多变，雕刻技艺高超。

　　和战国、汉代相比，魏晋时期的玉雕工艺水平大为下降，玉雕作品缺乏神韵，龙凤玉佩呈现线条简练、体态丰满的特点，但线条涩滞，缺乏战国、汉代玉佩线条有力、流畅的风格。而且在随后的历史中这种特点渐成主流风格，直至明清，无多大变化，浮雕龙凤图案题材的玉器也大体如此。到了明清时期，龙凤纹饰基本作为其他玉器的装饰，但也有少量龙凤玉佩饰。

　　夔是传说中的一种动物，形象似龙，只有一足。如果画成龙则为夔龙，画成凤则为夔凤，夔龙、夔凤佩主要流行于战国和汉代。

TAG:

Pacemaker was born of a blackout

Pacemaker was born of a blackout

The event that launched the medical electronics era was, ironically, an electrical blackout. Arriving in Minnesota's Twin Cities on the night of October 31, 1957, the blackout threatened the lives of a ward full of so-called "blue babies" at the University of Minnesota Hospitals, setting the stage for a medical revolution.

"One of the doctors lost a patient, and he asked for a better pacemaker immediately afterward," Earl Hatten, who served as a draftsman and engineer for Medtronic, Inc. for 35 years, told EE Times.

Four weeks later, Medtronic's founder and electrical engineer, Earl Bakken, delivered a crude, battery-powered pacemaker. Based on plans for a transistorized metronome that Bakken saw in Popular Electronics magazine, the new device replaced cart-based, ac-powered pacemakers with a design about the size of two cigarette packs. A day after delivering it, Bakken was stunned to find the unit hooked up to a little girl at the hospital.

"Mr. Bakken never saw what was coming," Hatten recalled. "In 1957, when Dr. (C. Walton) Lillehei asked him to make a portable pacemaker, it changed everything."

Indeed, the portable pacemaker transformed medicine. Using a few discrete elements, a battery, some crude electrodes and a pair of circuits to control signal frequency and amplitude, the first portable pacemakers took electrical therapy out of the hospital bed and into the outside world. By employing subtle electrical pulses to stimulate the heart's tissue, the devices saved lives. Early users hung them on their belts or around their necks. Today, about half a million of them are implanted inside patients' bodies annually.



Medtronic, now recognized as one of the world's biggest manufacturers of electronic medical systems, never set out to change the medical world, however. Bakken launched the company in a one-car garage with a box car attached to its back in 1949. Early employees repaired vacuum tube-based equipment inside the garage for 13 years, braving suffocating heat in the summers and huddling around oil-burning stoves to stay warm during frigid Twin Cities winters. For the most part, the company continued to exist as a medical equipment repair firm for eight years until the fateful blackout of Halloween Day, 1957, changed its fate.



Click on image to enlarge.Earl Bakken's portable, battery-powered pacemaker allowed cardiac patients to leave their hospital beds. (Source: Medtronic, Inc.)

TAG:pacemaker

Intel's 22-nm tri-gate SoC, how low can you leak?

Intel's 22-nm tri-gate SoC, how low can you leak?

SAN FRANCISCO -- Intel will describe its 22-nm tri-gate (FinFET) SoC technology for mobile applications Monday (Dec. 10) at the International Electron Devices Meeting (IEDM) here.

The chip maker introduced a CPU version of its 22-nm offering in June, but Intel senior fellow Mark Bohr said in an interview that the recipe has been tweaked in order to scale down to a more mobile, ultra-low leakage version.

The change means Intel will now be able to boast product support from high performance servers down to cell phones on a tri-gate 22-nm process, with transistors covering a wide range of performance barriers.



Intel’s new SoC technology also includes high voltage I/O transistors, precision resistors, capacitors and inductors that were not included on the original CPU version of the chip.

The SoC’s will be ready for high volume manufacturing in 2013, Bohr said.

Intel had tended to focus heavily on performance, but is now looking to widen its transistor scope. On the performance side of the scale is the CPU version of Ivy Bridge, which also exhibits higher power leakage. On the lower end of the scale, however, Intel is seeking to offering a range of choices.



“There isn’t just one version of our SoC technology," Bohr said. "We [will] offer a rich menu of options to pick and choose from, both different transistor options and different interconnect options,” said Bohr.



Next: Why FinFet is good for analog design
TAG:trigate finfet process technology fab

Imagination raises bid for MIPS

Imagination raises bid for MIPS

LONDON – Imagination Technologies Group, the graphics processor IP licensor, has raised its bid for processor IP company MIPS Technologies Inc. to $80 million in an attempt to outbid rival Ceva Inc.

Imagination (Kings Langley, England) originally bid $60 million to buy MIPS's operating business and certain patents while another U.K. company, ARM Holdings plc (Cambridge, England), would lead a consortium called Bridge Crossing that would acquire rights to major part of the MIPS portfolio of patents. Bridge Crossing would pay $350 million in cash to purchase the rights to the MIPS portfolio, of which ARM will contribute $167.5 million.

Ceva Inc. (Mountain View, Calif.) then offered $75 million for the operating business of MIPS (Sunnyvale, Calif.) on a similar basis to the Imagination bid.

Imagination said Monday (Dec. 10) that has signed a revised agreement for $80 million in cash with all the other terms and conditions of the acquisition remaining the same as for the previous bid.

In the year to June 30, 2012 MIPS made a loss before tax of $9 million on revenues of $60 million and on Sept. 30, 2012 MIPS had gross assets of about $20 million excluding cash and short-term investments, Imagination said. Imagination added that if its bid receives approval from MIPS' shareholders and meets other necessary conditions the deal is expected to complete during the first quarter of 2013.


Related links and articles:

www.imgtec.com

News articles:

Ceva bids for MIPS

ARM, Imagination divvy up MIPS

Top electronics business deals of 2012
TAG:Imagination MIPS Ceva IP license processor graphics DSP semiconductor

ST remains committed to FD-SOI, says CEO

ST remains committed to FD-SOI, says CEO

LONDON – Despite planning to sell or close ST-Ericsson, one of few users of its fully-depleted silicon on insulator (FDSOI) manufacturing process, STMicroelectronics has said intends to keep faith with the technology and continue manufacturing it at its wafer fab in Crolles, near Grenoble, France.

FDSOI would be one of three processes to be manufactured at Crolles, ST CEO Carlo Bozotti, told analysts on a conference call Monday (Dec. 10). The other two are CMOS with embedded non-volatile memory and CMOS for imaging sensors, Bozotti said.

STMicroelectronics NV (Geneva, Switzerland) told analysts on a conference call Monday (Dec. 10) that it intends to exit from its loss-making mobile digital chip joint-venture ST-Ericsson by the end of the third quarter 2013 but that it would continue to support ST-Ericsson with application processors, IP and manufacturing process technology during the disengagement. This will include the fully-depleted silicon-on-insulator (FD-SOI) process which ST has pioneered at 28-nm and with a road-map to 20-nm.

"Clearly we have the opportunity to move on with our FDSOI kind of technology, differentiated technology for low power applications in consumer products," Bozotti said on the call, adding: "It is only one of three pillars for Crolles."

The FDSOI process is claimed to have advantages for smartphone and tablet computer digital ICs in terms of the trade-offs between performance, power consumption and manufacturability. However, ST's primary customer for the FDSOI process at 28-nm and going to 20-nm, is the heavily loss-making ST-Ericsson. Most other companies are making use of planar bulk CMOS at 28-nm and 20-nm from foundries with plans to go to a FinFET-based manufacturing process at 16-nm. The world's largest chip company Intel has already introduced a FinFET-based manufacturing process at 22-nm.

The FDSOI manufacturing process technology has been selected by ST-Ericsson for its NovaThor mobile phone platform with 28-nm FDSOI prototyping in July 2012 and 20-nm FDSOI due to be ready for prototyping by 3Q13. In addition, ST has a licensing agreement with foundry Globalfoundries Inc. (Milpitas, Calif.) to be a FDSOI production and to open up the process to more customers.

When asked about manufacturing strategy as ST moves forward from the disposal of its holding in ST-Ericsson, Bozotti told analysts that ST would move on with FDSOI technology for low power in consumer products. Bozotti added that FDSOI was part of a three-legged manufacturing strategy for Crolles, all fundamental for the future of the company.

The first pillar is CMOS with non-volatile memory. Crolles is already manufacturing this process at 55-nm and would be moving to 40-nm, Bozotti said. He added that the process is good for general purpose, secure microcontrollers and automotive microcontrollers and that all production would move to 300-mm wafers and be responsible for about one-third of production at Crolles.

The second process is CMOS for imaging sensors – a part of ST's business that had been under a strategic review in 2010. At that time it had been decided to adopt a policy of application diversification and that this has been successful, Bozotti said. ST has multiple design wins in automotive and elsewhere, he added. The third manufacturing platform at Crolles would be FDSOI applied to digital consumer and ASIC products, Bozotti said.


Related links and articles:

www.st.com

News articles:

ST to exit ST-Ericsson in 2013

ST-Ericsson vows to keep working on turnaround

London Calling: Should Apple buy ST-E or Renesas Mobile?

ST opens up 28-nm, 20-nm FDSOI with Globalfoundries




TAG:ST ST Ericsson STMicroelectronics FDSOI Soitec semiconductor maufacturing process mobile tablet smartphone

ST remains committed to FDSOI, says CEO

ST remains committed to FDSOI, says CEO

LONDON – Despite planning to sell or close ST-Ericsson, one of few users of its fully-depleted silicon on insulator (FDSOI) manufacturing process, STMicroelectronics has said intends to keep faith with the technology and continue manufacturing it at its wafer fab in Crolles, near Grenoble, France.

FDSOI would be one of three processes to be manufactured at Crolles, ST CEO Carlo Bozotti, told analysts on a conference call Monday (Dec. 10). The other two are CMOS with embedded non-volatile memory and CMOS for imaging sensors, Bozotti said.

STMicroelectronics NV (Geneva, Switzerland) told analysts on a conference call Monday (Dec. 10) that it intends to exit from its loss-making mobile digital chip joint-venture ST-Ericsson by the end of the third quarter 2013 but that it would continue to support ST-Ericsson with application processors, IP and manufacturing process technology during the disengagement. This will include the fully-depleted silicon-on-insulator (FD-SOI) process which ST has pioneered at 28-nm and with a road-map to 20-nm.

"Clearly we have the opportunity to move on with our FDSOI kind of technology, differentiated technology for low power applications in consumer products," Bozotti said on the call, adding: "It is only one of three pillars for Crolles."

The FDSOI process is claimed to have advantages for smartphone and tablet computer digital ICs in terms of the trade-offs between performance, power consumption and manufacturability. However, ST's primary customer for the FDSOI process at 28-nm and going to 20-nm, is the heavily loss-making ST-Ericsson. Most other companies are making use of planar bulk CMOS at 28-nm and 20-nm from foundries with plans to go to a FinFET-based manufacturing process at 16-nm. The world's largest chip company Intel has already introduced a FinFET-based manufacturing process at 22-nm.

The FDSOI manufacturing process technology has been selected by ST-Ericsson for its NovaThor mobile phone platform with 28-nm FDSOI prototyping in July 2012 and 20-nm FDSOI due to be ready for prototyping by 3Q13. In addition, ST has a licensing agreement with foundry Globalfoundries Inc. (Milpitas, Calif.) to be a FDSOI production and to open up the process to more customers.

When asked about manufacturing strategy as ST moves forward from the disposal of its holding in ST-Ericsson, Bozotti told analysts that ST would move on with FDSOI technology for low power in consumer products. Bozotti added that FDSOI was part of a three-legged manufacturing strategy for Crolles, all fundamental for the future of the company.

The first pillar is CMOS with non-volatile memory. Crolles is already manufacturing this process at 55-nm and would be moving to 40-nm, Bozotti said. He added that the process is good for general purpose, secure microcontrollers and automotive microcontrollers and that all production would move to 300-mm wafers and be responsible for about one-third of production at Crolles.

The second process is CMOS for imaging sensors – a part of ST's business that had been under a strategic review in 2010. At that time it had been decided to adopt a policy of application diversification and that this has been successful, Bozotti said. ST has multiple design wins in automotive and elsewhere, he added. The third manufacturing platform at Crolles would be FDSOI applied to digital consumer and ASIC products, Bozotti said.


Related links and articles:

www.st.com

News articles:

ST to exit ST-Ericsson in 2013

ST-Ericsson vows to keep working on turnaround

London Calling: Should Apple buy ST-E or Renesas Mobile?

ST opens up 28-nm, 20-nm FDSOI with Globalfoundries




TAG:ST ST Ericsson STMicroelectronics FDSOI Soitec semiconductor maufacturing process mobile tablet smartphone

ST to exit ST-Ericsson in 2013

ST to exit ST-Ericsson in 2013

LONDON – As part of a strategic plan to improve its financial situation European chip comapny STMicroelectronics has announced its intention to exit from its mobile digital joint venture ST-Ericsson. ST announced in a conference call Monday (Dec. 10) that it intends to have left the joint-venture by the end of the third quarter of 2013 and that it is already in negotiations on the options.

At the same time CEO Carlo Bozotti told analysts that ST would focus on five key product areas where it already leads in the global market or where it can soon be the leader. These five product areas are MEMS and sensors, smart power, automotive electronics, microcontrollers and application processors for digital consumer.

In the area of application processors ST will abandon the mobile digital sector but continue to make set-top-box chips, cable modems, DisplayPort connection chips, network processors, car infotainment and ASICs for gaming.

As part of the re-organization ST will be divided into two product segment groups: sensors, smart power and automotive and embedded processing, Bozotti said. Both segments are expected to be profitable and cash generating.

ST said the changes will reduce the company's quarterly net operating expenses from about $900 million to between $600 million and $650 million by the beginning of 2014 excluding restructuring charges. The business would target 10 percent or more operating margin.

"Mobile broadband is a very important market but not for ST," Bozotti told analysts during the conference call.

ST said it will continue to support ST-Ericsson with application processors, IP and manufacturing process technology during the disengagement. This will include the fully-depleted silicon-on-insulator (FD-SOI) process which ST has pioneered at 28-nm and with a road-map to 20-nm.

Meanwhile will not abandon the mobile digital market altogether. It will still manufacture motion, environmental, image and touch sensors for that market; as well as audio amplifiers, microphones, secure microcontrollers, AMOLED display drivers.

However, Bozotti and ST declined to comment on the current value of the ST-Ericsson joint venture or what sort of costs disposal of ST-Ericsson would incur if it could not achieve a sale of the business.

ST-Ericsson has been losing several hundred millions of dollars per quarter since its formation in February 2009 and has built up large debts with its parent companies. Bozotti said that ST-Ericsson had been caught out by a dramatic change in the mobile digital equipment market that started about two years ago with changes in operating system and a trend towards vertical integration amongst certain market leading companies. ST-Ericsson had also suffered because of change at a former major customer of ST's, Bozotti said.


Related links and articles:

www.st.com

News articles:

Analysis: ST-Ericsson rescue plan underwhelms

How long has ST-Ericsson got?

Why ST should sell ST-Ericsson to China


TAG:STMicroelectronics ST ST Ericsson semiconductor mobile digital processor

London Calling: Russia must deliver on tech investment

London Calling: Russia must deliver on tech investment

Russian credibility in electronics has long been low. Too many government plans have been announced and not fulfilled. When Russia received a windfall through the export of oil, gas and other energy resources, it gained some serious money for technology investment.

Russia seemed prepared to invest its new-found wealth in a couple of Soviet-era chip companies: Mikron JSC and Angstrem JSC, supporting plans to bring in older manufacturing processes from the likes of STMicroelectronics and Advanced Micro Devices. But then in 2009, Sitronics, the owner of Mikron, shelved plans to build a 300-mm wafer fab equipped with 65- and 45-nm manufacturing processes. The project was supposedly intended to launch in 2010 but was delayed by the global recession.

With the creation of Russia Corporation of Nanotechnologies (Rusnano), investment policy appeared to shift. The plan seemed to be using energy export funds to attract capital-starved western companies to put down manufacturing roots in Russia, thereby importing current technology while creating jobs and infrastructure.

The list of announced deals is growing long and expensive:

• 2008: Russia's Onexim forms LED lighting joint venture (Optogan)
• 2010: Rusnano invests in Plastic Logic for Russia (thought to be worth $300 million in the short term, $700 million in the long-term)
• 2011: Russia backs MRAM startup Crocus ($250 million)
• 2011 Rusnano draws MEMS firm SiTime to Russia ($15 million)
• 2012 Rusnano helps close $79 million Quantenna deal
• 2012 NeoPhotonics deals with Rusnano, plans facilities in Russia ($40 million)
• 2012 Aquantia closes $35 million Series F funding round
• 2012 Russia backs Mapper e-beam lithography firm (about $50 million)

Next: ROI, please
TAG:Peter Clarke London Calling Plastic Logic Rusnano semiconductor Crocus MRAM SMIC Optogan

翡翠珠宝价格再创新纪录

翡翠珠宝价格再创新纪录

一条翡翠珠链拍出了1.06亿港元的天价。日前，天成国际2012年珠宝及翡翠秋拍上，这条罕见的有23粒大颗天然翡翠珠链的成交价，刷新了翡翠单件珠宝拍卖的世界纪录。而翡翠收藏价值及保值功能也再度引起关注。

　　一条翡翠珠链拍出了1.06亿港元的天价。日前，天成国际2012年珠宝及翡翠秋拍上，这条罕见的有23粒大颗天然翡翠珠链的成交价，刷新了翡翠单件珠宝拍卖的世界纪录。而翡翠收藏价值及保值功能也再度引起关注。

　　在这串翡翠珠链“创纪录”的背后，是翡翠价格近两年“过山车”似的变化。业内人士介绍，在过去一年多的时间里，我国内地中低档翡翠的价格上涨了30%到50%，而一些高档翡翠更是涨了5至10倍，并在2011年初达到顶峰。但随后剧烈的暴跌也让不少人记忆犹新。

　　从行内人士眼中看来，翡翠的价格这几年实际上是稳步上升的。前几年由于经济向好，一些行外如地产界的热钱流向了翡翠市场。

　　“不懂行的人在拍卖会上喊高价，而原石价格也是就高不就低，翡翠市场才出现了假繁荣的现象。”2011年底经济形势转弱，行外投资者纷纷抛售，贱卖也成必然，催化着翡翠价格急剧走低。“但是好的东西，一直都在涨价。”

　　如果想要具有收藏价值和保值功能的翡翠，中国青年翡翠艺术大师表示，要挑选“对的东西”。要么是翡翠本身的质地十分完美，要么就是在翡翠加工的工艺上十分精湛，“说白了就是要收藏精品。”

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Renesas puts smart home operating system into play

Renesas puts smart home operating system into play

Renesas is looking to combine all its software for the smart home on one real time operating system, which may be developed in-house or acquired.

"Renesas has decided to have more focus on the stable microcontroller business," said Shigeo Mizugaki senior VP and member of the board of Renesas, speaking at the Electronica trade show in Germany. "We are intending to expand our technologies to the smart society. Renesas will prepare the HMI and interoperability with the stacks such as sensors, HVAC air conditioning and Ethernet." This will be integrated under one RTOS.

"We are now starting discussions to get the capabilities with third parties," he said. The company has renegotiated its short term debt and obtained additional funding from four Japanese banks and major stakeholders which will give cash for acquisitions. "Getting the money for new growth means acquisition is a strong option," he said.

As the largest microcontroller supplier with 27% market share across industrial, home and automotive the choice of a single operating system across multiple markets will be significant for embedded software developers.

The move also demonstrates a move to the 32bit RX family of microcontrollers combined with analog peripherals and Renesas' MONOS embedded flash which has already taped out at 40nm and a 28nm version is in development and can scale further, says Mizugaki.

http://www.renesas.com

This article originally appeared on EE Times Europe.

TAG:smart home operating system renesas MCU RTOS

Wireless LAN market posts record quarter revenues

Wireless LAN market posts record quarter revenues

A recently published report by Dell'Oro Group revealed the Wireless LAN (WLAN) market posted record revenues in the third quarter, and a 19 percent revenue growth over the same period last year. This strong industry performance was further underlined by eight WLAN vendors who achieved their highest ever quarterly results.

"Three trends are now driving faster-than-industry growth in the enterprise WLAN segment - devices that are cloud-managed, those optimized for use by Service Providers, and systems that leverage software to integrate wireless and wired infrastructures," explained Chris DePuy, Analyst of Wireless LAN research at Dell'Oro Group. "We see vendors focusing innovation dollars and marketing efforts to aggressively pursue these three areas," said DePuy.

In the third quarter, Cisco Systems maintained the majority revenue market share in the Enterprise WLAN market, followed by Aruba Networks and Hewlett-Packard. In the SOHO market, NETGEAR retained the number one revenue rank, followed by Technicolor. In the Service Provider WiFi market, Cisco Systems, Ruckus Wireless and Hewlett-Packard were the top three vendors by revenue.

http://www.DellOro.com

This article originally appeared on EE Times Europe.

TAG:Wireless LAN market WLAN market research

Global cellular M2M connections to grow to over 325 million by 2016

Global cellular M2M connections to grow to over 325 million by 2016

IMS Research forecasts the market for cellular machine-to-machine (M2M) connectivity services to rise from approximately 107 million connections globally in 2011 to about 326 million connections by 2016. Mobile operators are intently focused on developing and expanding their activities in the cellular M2M market as a key growth opportunity in the face of increasing saturation and maturity of the core mobile voice/data services market.

A number of factors are enabling and driving cellular M2M market growth including: government regulatory initiatives (such as eCall in the European Union), the desire by corporate adopters to increase efficiency and develop new revenue models, the increasing number of tools and platforms that help to facilitate cellular M2M application development and the declining costs of components and services (including connectivity). Mobile operators have become key players in facilitating cellular M2M market growth, by establishing M2M business units, deploying connection management platforms (CMP) and taking a leading role in coordinating the cellular M2M value chain at multiple levels.

According to Sam Lucero, senior principal analyst at IMS Research, "Mobile operators are not simply providing managed connectivity services to the cellular M2M market but increasingly are 'connecting the dots' among M2M ecosystem players, including suppliers and developers — and this benefits the market as a whole. Examples of this proactive role by mobile operators range from establishing module supply programs to developing partnerships with platform vendors and solution suppliers to reduce overall complexity in the value chain."

Mobile operators are providing leadership in the cellular M2M market not only to grow the overall market, including the opportunity for offering managed connectivity services to M2M application service providers (ASPs), original equipment manufacturers (OEMs) and corporate adopters, but also to expand the mobile operators' own share of the M2M value stack. IMS Research estimates that managed connectivity accounts for only about 10 – 30 percent of the overall value in the M2M service value chain. Consequently, mobile operators are seeking to provide more value through the provisioning of value-added services to solution developers and end-to-end applications to end-users, typically through partnerships with ASPs.

A recent example of this trend toward solution enablement and ecosystem facilitation is the Telefonica Digital announcement which was made at the Smart City Expo World Congress, regarding the operator's Smart Cities solution offering. As Telefonica Digital highlighted in their announcement: "It is an offering which will allow municipal corporations, urban service providers and entrepreneurs worldwide to integrate in a single scalable, flexible and self-managing solution the complex environment of necessary sensors and technology, which are characteristic of so-called "Smart Cities."

http://www.ihs.com

This article originally appeared on EE Times Europe.

TAG:cellular M2M machine to machine smart cities market research

明清玉器逆市上扬新玉投资大有市场

明清玉器逆市上扬新玉投资大有市场

尽管今年艺术品市场整体走势低迷，部分玉器拍卖也呈现出萎缩态势，但是明清玉器精品的收藏和投资价值仍旧通过了市场的严峻考验。新玉的投资和收藏也很活跃，多数玉雕大师手上的活儿已经预约到了三至五年之后，而买家对当代精品玉器其实从未吝啬过。 　　尽管今年艺术品市场整体走势低迷，部分玉器拍卖也呈现出萎缩态势，但是明清玉器精品的收藏和投资价值仍旧通过了市场的严峻考验。新玉的投资和收藏也很活跃，多数玉雕大师手上的活儿已经预约到了三至五年之后，而买家对当代精品玉器其实从未吝啬过。

　　市场青睐明清玉器精品

　　虽然今年艺术品市场整体走势低迷，部分玉器拍卖也呈现出萎缩态势，但是明清玉器精品的收藏和投资价值仍旧通过了市场的严峻考验。采访中记者了解到，明清玉器艺术造诣高，而且具备稀缺性、不可再生性和耐久性的优秀品质，市场表现良好。在古玉市场，明清宫廷玉器仍是主流。这一时期的玉器精品大都流传有序，受市场环境影响不大。

　　新玉投资大有市场

　　某拍卖公司负责人告诉记者，相比明清玉器坚挺的市场表现，当代玉雕作品略显逊色。“北京匡时的当代玉雕大师作品专场成交率为46%，虽然成绩有所下滑，但当代艺术大师的作品价格却得到了买家的广泛认可。”

　　对此，玉石收藏家并不认同新玉收藏市场存在滞后性，“当代大师玉雕精品之所以流通量少，是因为在进入拍卖领域之前，就已经被藏家收购了。藏家往往会拿出自己的优质原石，专门请大师设计和雕刻，而且多数玉雕大师手上的活儿已经预约到了三至五年之后，雕琢成才的作品短期内不会进入流通领域。其实买家对当代精品玉器从未吝啬过。2011年一组由中国玉石雕刻大师吴德升创作的青史香尘白玉摆件，在西泠春拍中拍出了1035万元的天价，创造了中国当代玉雕拍卖的最高纪录，也对当代玉器的收藏产生了深远影响。”

　　“当代玉器高端藏品所占的市场份额不足20%。”和田玉市场可细分为三类。第一类商品处于金字塔底部，市场份额超过50%，此类产品其质地、文化含量、工艺价值都无关紧要，档次较低。第二类是玩赏品，讲究品质、雕工和题材，市场占有率为30%，多亮相于藏家之间的交流鉴赏。新玉市场金字塔顶端的是收藏品，此类多为当代艺术大师的玉雕精品或是获奖作品，原料稀缺，雕工精致、富有创意，彰显了作者个人的艺术风貌。当代玉雕名家是历代制玉者中最具专业基础的人，他们正规系统的美术、设计教育根基对其创作影响深远，他们将绘画、雕塑、书法、石刻、民俗和当代艺术的精髓运用于玉雕创作，作品风格亦古亦今。”

　　莫入投资误区

　　随着当代玉器在拍卖市场逐渐崭露头角，对于新玉的收藏及鉴赏标准也出现了分化。“目前藏家对于当代玉器的鉴赏存在诸多误区。首先，赏白不赏脂，重脂不重润。和田玉最珍贵的品质是细腻温润，而非色泽有多白皙。其次是赏皮不赏质。和田玉留皮色重巧雕很重要的原因是为了提供其为籽料的佐证，但是皮色依附于玉肉之上，二者相得益彰，只重皮色则过犹不及。此外，赏料不赏工也不可取。玉不琢不成器。玉器的雕刻工艺决定了它的艺术内涵和市场附加值，那些为了快速变现而一味追逐原石的藏家，最终会被市场淘汰。最后是赏地不赏质，对原石的产地过于纠结也不对，即便是和田出产的玉石也有品质优劣之分，并非所有的和田玉都是精品。”

　　玉文化的内涵支撑着中国人对玉器的独特情结，也影响着当代玉器作品的审美标准。“藏家对新玉的审美水平正在不断提高，他们开始注重作品的工艺、创意和艺术价值。一件真正优秀的玉雕作品，造型应该是基于原料形质的巧妙设计，雕琢应该是基于皮色层次的巧雕，艺术风格应该融合了作者对时代特色的理解。”

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